4. Example features

4.1. Clocks evaluation

Programmable clocks evaluation in receiver mode

1. Set receiver mode

• Click on the button in the left corner of the navigation bar and select core
• Select RX chip mode button in Chip mode section

2. Select two phase shifter channels one with fine phase shifting

• Click on the button in the left corner of the navigation bar and select clocks
• Select a frequency button to activate channels
• Set Enable in Fine Tune to enable fine phase shifting for one phase shifter (resolution = 48.8 ps)

3. Program different options the phase shift of the channels

• Click on phase slider to program different options for the phase shifter
• Changes can be observed with a scope
• Click on the Settings button to enabled advanced configuration options
• Click on drive strength to select an amplitude
• If phase control tune button is disabled you will program coarsely the phase for the channel (resolution = 781.25 ps)
• Fine phase setting is disabled by default

4.2. PLL performance evaluation

Evaluation of the PLL performance

1. Configure lpGBT in external 40 MHz reference clock

• Set lockmode switch to 0 on LpGBT characterization board

2. Configure lpGBT in simple TX mode

• Click on menu bar in the top left corner of the screen and select Core
• Select TX chip mode
• Select transmitter mode data rate and FEC encoding

3. Configure 1 eclock @320 MHz, 2 mA drive strength and no pre-emphasis

• Click on the menu bar in the top left corner of the screen and select Clocks
• For EPCLKn select 320 MHz frequency button
• Click on setting button to access to the advanced configuration (not implemented)
• Select drive strength 2.0 mA amplitude
• Select disable pre-emphasis mode

4. Change PLL parameters(charge pump current and resistors values) (not implemented)

• In PLL configuration division select PLL charge pump current to set current value
• Select PLL resistor value

4.3. Transceiver configuration

1. Set transceiver mode at 5Gbps data rate and FEC12 encoding

• Click on the menu bar in the top left corner of the screen and select Core
• Select TRX chip mode button then 5Gps and FEC12 button

2. Enable all uplink elinks with data rate @320Mbps, auto phase selection and enabled termination

• Select 320 data rate button
• Auto phase selection is set by default for all uplinks
• Select TERM button

3. Enable 4 downlinks elinks at 160Mbps with 2 mA amplitude and no pre-emphasis

• Select 160 data rate button
• Click on drive strength option and select 2.0 to set 2 mA amplitude
• Click on pre-emphasis option and select disable

4. Configure 2 eClocks at 320MHz with 2 mA amplitude and no pre-emphasis

• Click on the menu bar in the top left corner of the screen and select Clocks
• Go to eclocks number to configure then select 320 Frequency button
• Click on drive strength option and select 2.0 to set 2mA amplitude
• Click on pre-emphasis option and select disable

5. Configure 2 eClocks @320MHz delayed by 10ns with 2 mA amplitude and no pre-emphasis

• Go to eclocks number to configure then select 320 Frequency button
• Click on phase slider and move the cursor to set phase value at 10ns
• Click on drive strength option and select 2.0 to set 2mA amplitude
• Click on pre-emphasis option and select disable

6. Enable RSTOUTB with 100 ns pulse duration (not implemented)

• Click on the menu bar in the top left corner of the screen and select Status
• Go to LpGBT reset out section
• Click on phase duration select option for rstoutb and select 100
• Click on Reset button to generate the pulse

7. Example of LpGBT I2CM1 communication with slave connected

• Click on the menu bar in the top left corner of the screen and select I2C Master number
• Enter slave address in hexadecimal 0x51
• Select 8-bit register address width
• Enter register address in hexadecimal 0x00
• Set Bus Speed to 400 kHz
• In Write division enter the data to write 0x01
• Click on the write button
• Repeat the process for each slave address register to configure

8. Check if downlink high speed is locked

• In the top right corner of the screen the spinner is green if downlink high-speed data are locked

9. Check if elinks receivers are locked and the phase selected

• Reloading the page will automatically read back the register value and set the page according to register configuration
• Click on menu bar and Status
• Read status lock and current phase for EPRX group/channel (not implemented)

4.4. Transmitter configuration

1. Set transmitter mode at 10Gbps data rate and FEC5 encoding

• Click on the menu bar in the top left corner of the screen and select Core
• Select TX chip mode button then 10Gbps and FEC5 button

2. Enable all uplink elinks with data rate at 1280Mbps auto phase selection and enabled termination

• Select 1280 data rate button
• Auto phase selection is set by default for all uplinks
• Select TERM button to activate termination

4.5. Analog peripherals configuration

1. Enable internal voltage reference

• Click on the menu bar in the top left corner of the screen and select analog
• Select Generator Enable button
• Select slider to tune voltage value

2. Set Voltage DAC to 0.63 V

• In Voltage DAC section select Enable
• Click on voltage DAC value slider and set voltage (Vout=(VOLDACValue/4096)*vref)

3. Monitor VDD inside the chip

• In ADC section clock on VDD monitoring
• Select VDD source in ADC positive input selector
• Click on start conversion button to read ADC value

3. Read back temperature sensor

• Go to ADC Temperature Sensor section
• Click on Measure Temperature button to start internal sensor temperature measurement
• Read temperature from ADC is the sensor temperature in degree Celsius

4. Read resistance of PT1000 sensor connected to ADCn channel

• In current DAC section, enable CDAC current
• Select current DAC slider and set current value
• Connect sensor to correct ADC pin
• In Voltage ADC section select ADC pin used in ADC positive input selector
• Read ADC value of PT1000 sensor resistance conversion

4.6. Evaluation of high-speed uplink

1. Configure lpGBT in external 40 MHz reference clock

• Set lock mode switch to External lock mode on the VLDB+ board

2. Configuration PRBS7 in the serializer

• Click on the menu bar in the top left corner of the screen and select test features
• Select PRBS7 generator in Uplink Serializer Data Source

3. Modulation current and pre-emphasis monitoring for line driver

• Click on the menu bar in the top left corner of the screen and select high-speed
• Select modulation current slider to monitor the current in Line driver section
• To activate pre-emphasis driver click on Enable
• Select pulse width of pre-emphasis: Long (60 ps) or Short (40 ps)

4.7. Evaluation of high-speed downlink

1. External PRBS7 sequence generator connected to RX inputs of lpGBT

• Click on the menu bar in the top left corner of the screen and select test Core
• Select RX chip mode

2. Equalizer settings and eye diagram measurement

• Click on the menu bar in the top left corner of the screen and select high-speed
• Select attenuation value, programmable attenuator can provide attenuation of 0 dB, -3.6 dB or -9.5 dB
• Select a value for the capacitance
• Select a value for resistors 1 to 4

3. Run a bit error test

• Click on the menu bar in the top left corner of the screen and select test features
• In BERT Pattern Checker select data source to be checked
• Select reference channel signal for pattern checker
• Set the duration of the measurement
• Start BERT measurement
• Read BERT result

4.8. Access to raw values of registers

• Click on the menu bar in the top left corner of the screen and select Registers
• On register map filter, enter register name or register address to read
• To modify register value, click on register name on the list and enter a new value

• Example: To disable the watchdog enter POWERUP0 in the Register map search bar

  Click on the register name in the list Set bit 7 PUSMpllWdogDisable to 1 in the Update Register Value window